By P. Chu
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Extra resources for Advances in Solid State Circuits Technologies
DRP chips (4). They include reconfiguration memories and a microprocessor array on a single chip. The internal reconfiguration memory stores the reconfiguration contexts of 16 banks, which can be substituted for one another during a clock cycle. Consequently, the arithmetic logic unit can be reconfigured on every clock cycle in a few nanoseconds. Unfortunately, increasing the internal reconfiguration memory while maintaining the number of processors is extremely difficult. As with other rapidly reconfigurable devices, optically reconfigurable gate arrays (ORGAs) have been developed, which combine a holographic memory and an optically programmable gate array VLSI, as portrayed in Figs.
Watanabe, F. Kobayashi, ”Optically Differential Reconfigurable Gate Array,” Electronics and Computers in Japan, Part II, Issue 11, vol. 90, pp. 132-139, 2007.  M. Nakajima, M. Watanabe, ”A four-context optically differential reconfigurable gate array,” IEEE/OSA Journal of Lightwave Technology, Vol. 27, No. 24, 2009.  M. Watanabe, F. Kobayashi, ”Dynamic Optically Reconfigurable Gate Array,” Japanese Journal of Applied Physics, Vol. 45, No. 4B, pp. 3510-3515, 2006.  D. Seto, M. Watanabe, ”A dynamic optically reconfigurable gate array – perfect emulation,” IEEE Journal of Quantum Electronics, Vol.
7V In Fig. 11. it shows the drain-source voltage of the input transistors M1 and M2, VDS1 and VDS2, changes with the input voltage. Within ±1V input voltage, VDS1 and VDS2 are very small. According to equation (40), VDS1 and VDS2 are too small such that transistors M1 and M2 can be set in triode region. Once the input voltage exceeds ±1V, VDS1 and VDS2 will increase rapidly. It results in that transistors M1 and M2 enter in saturation region. In other words, when M1 and M2 entering saturation region the proposed transconductor can not maintain the high linearity.